A New MSB Modular multiplication Algorithm and its Implementation using 4-2 Compressor

Abstract

Currently, enhancing the performance of modular multiplication is very important for high performance
microprocessors. Multiplication is inherently a slow operation as a large number of partial products. In this paper,
Implementation of MSB modular multiplication using 4-2 compressor using the last two most significant bits is
introduced. Using the two most significant bits (MSB's) for reduction in this technique, we will avoid the use of
the carrier so, no carry store. However, we don’t need to use the feedback which used in Montgomery
Multiplication [13]. The total power-efficiency (power-delay-product) is reduced using low-power low-voltage 4-2
compressors. The circuits implemented using Matlab simulation.